Short module programs are a great way to complement your knowledge with industry centric VLSI programs and prepare you for a great career, while keeping your day job. Currently four modules spanning the RTL to gds design cycle are offered. Students in final year of engineering can benefit from these programs too.
All modules are self contained and start from basic core concepts to advanced topics, meant to give you a handle on the subject. All modules have a good mix of theory and lab and are conducted in an evaluated learning atmosphere.
Industry standard EDA tools from Synopsys, Cadence and Mentor Graphics are used.
Foundry digital kits from Jazz Semiconductors, USA., will be used. Solaris/Linux machines from Sun Microsystems will be used.
Major portion of the time is spent gaining hands on experience using EDA tools to solve problems.
All students will have access to a computer and EDA tools on a 1:1 basis during the labs to enhance the effectiveness and to maintain quality of our programs.
| Program 1: Linux and perl scripting for VLSI Engineers (SMPLINPM) - 80 Hours |
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Course Objective:
This program introduced students to the UNIX/Linux environment and perl language. After completion of this program students will have gained working knowledge of Linux and scripting.
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- Introduction to Linux
- Shell programming
- Fundamentals of Perl programming
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Who should take this program:
Under grad and post grad students working on VLSI projects, Working professionals with limited knowledge of Linux. CAD engineers in VLSI companies.
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| Program 2: Hardware design using Verilog and VHDL (SMPRTLAM) - 80 Hours |
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Course Objective:
Gain exposure to RTL coding and verification. Basic to advanced concepts in RTL coding & verification. Different coding styles for FPGA VS ASIC implementation. After completion of this program students will have a good knowledge of coding requirements for verification, synthesis and RTL verification techniques.
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- Introduction to VHDL and Verilog
- Logic design, RTL coding, analysis, synthesis flow and optimization techniques
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- RTL stimulation and verification
- High level Modeling techniques using Vera
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Who should take this program:
Working professionals new to RTL verification and/or need a refresher course. Under grad, post grad students interested in RTL verification careers, students working on verification projects as part of UG, PG course.
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| Program 3: ASIC Implementation – RTL to Netlist (SMPAFEAM) - 80 hours |
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Course Objective:
Gain exposure to ASIC frontend implementation. Basic to advanced topics in RTL synthesis, tehchiques, DFT, Static timing analysis and formal verification will be covered. After completion of this programs students will have a good knowledge of the forntend flow and various techniques used by professionals to meet design specifications
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- Logic design, RTL coding, analysis, synthesis flow and optimization techniques
- Static Timing Analysis
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- Design For Test (DFT)
- Formal Verification
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Who should take this Program:
Working professional new to ASIC methodology, Students interested in pursuing FPGA or ASIC design careers, students working on VLSI projects as part of UG or PG course
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| Program 4: ASIC Implementation – Netlist to GDS (SMPABEPM) - 80 Hours |
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Course Objective:
Gain exposure to ASIC backend implementation. Basic to advanced topics in Floorplanning, Placement, CTS, routing and physical verification, parasitic extraction and back annotation will be covered. After completion of this programs students will have a good knowledge of the backend flow and various techniques used by professionals to meet design specifications |
- Overview of IC fabrication process
- CMOS devices, operation, layout views
- Introduction to Foundation IP
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- Timing Driven Place and Route flow
- Floor planning, Placement, CTS
- Routing, DRC, LVS and parasitic extraction & BA
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Who should take this Program:
Working professional new to ASIC backend methodology, Students interested in pursuing ASIC backend careers, students working on VLSI projects as part of UG or PG course
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For Short Module Program
Eligibility: 7th Sem BE in IT related disciplines
3rd Sem M.Tech in VLSI or related discipline
M.Sc, B.Sc. students from science/VLSI background
Working professionals in related fields
Selection Process: Interview and counseling
Timings: Monday to Friday 8.30am to 10.30 am
6.00pm to 8.00pm
Saturday 10.00am to 1.00pm
2.00pm to 6.00pm
Fees: Rs.750 Application Fees
Managements reserves the right to grant admissions to all programs.
In an effort to maintain quality and meet changing needs of the industry management reserves the right to change course contents, duration and fees at any time.
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