This program offers IC mask layout training enabling students to gain mastery and technical expertise in this specialized area. The course covers all aspects of IC mask layout, starting from electrical concepts to advanced topics in deep sub micron, as appropriate for layout design. Conducted by industry professionals, the program is delivered in an industry like atmosphere using Sun Solaris/Linux machines and industry standard EDA tools from Cadence and Mentor Graphics and Foundry kits from Jazz Semiconductors, USA.
A good balance of lectures and labs, followed by live projects ensures a highly interactive learning experience.
| COURSE CONTENTS: |
- Introduction to Linux
- IC process overview
- Basic CMOS device operation
- CMOS device construction
- Introduction in Layout editors and process design kits
- Layout styles for Analog and digital designs
|
- Layout optimization techniques to reduce area and parasitics
- IP handoff guidelines for foundation IP and Analog layouts
- Physical verification and extraction
- Nanometer effects and DFM rules
- ESD, LUP
- Layout porting
|
Eligibility: Diploma in Electronics, BE in IT related area
Entry requirement: Written test and interview
Timings: Monday to Friday 10.00am to 6.00pm (Full time) Duration 4 weeks
|
