This program offers VLSI training as relevant to ASIC Design, enabling students to gain mastery and technical expertise in this specialized area of VLSI Design. The course builds from core concepts to advanced levels with a good balance of lectures and labs, followed by a live project. Conducted by a team of highly dedicated industry professionals and faculty trained by them, the program is delivered in an industry like atmosphere using Sun cluster grid, thin client technology and industry standard EDA tools from Cadence Synopsys and Mentor Graphics and Foundry kits from Jazz Semiconductors, USA..
Phase I
Revisit VLSI Design from a perspective, as needed to work in the industry. Correlate application of knowledge to solve design problems during this phase. Students get the opportunity to gain hands on experience using EDA tools to solve simple problems.
Phase II
Building upon phase I this phase introduces students to advanced topics in ASIC design, beyond what is normally covered in most regular UG, PG programs. During this phase students are assigned to teams based on aptitude, and work on projects that require application of theoretical knowledge to solve problems, using industry standard EDA tools.
Phase III
Each student takes ownership of a block and is accountable for meeting deadlines, and working with other members in the design team. Students will participate in design reviews and receive regular feedback from experts and industry professionals. Upon successful completion of projects diploma certificate will be awarded.
Course Contents
| Phase I: Foundation Program - 4 Weeks |
- Linux and perl for VLSI Engineers
- Semiconductor and CMOS theory, IC process for VLSI Engineers
- Fundamentals of digital design and introduction to foundation IP
- Hardware design using Verilog HDL, RTL verification
- ASIC Implementation – I RTL to netlist
- ASIC Implementation – II Netlist to gds
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Phase II: Advanced topics in ASIC Design - 4 Weeks
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- RTL coding, analysis, synthesis flow and optimization techniques
- Block & chip level verification
- High Level Modeling & verification techniques
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- RTL coding, analysis, synthesis flow and optimization techniques
- Advanced timing concepts and analysis
- Design For Test & Formal Verification
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- IC process, 2.5D, 3D extraction models
- Foundation IP used in ASIC design
- Floor planning, placement, CTS & routing concepts, objectives and strategies, for Analog mix signal IC’s
- Parasitic Extraction & BA, DRC, LVS
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Phase III: Live Project - Upto 8 Weeks
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- Task assignment to teams
- Daily status meeting to identify issues and explore possible solutions
- Design review and documentation
- Tape out, archiving and documentation
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In an effort to maintain quality and to stay current, per changing needs of industry, program contents and duration are subject to change anytime.
Eligibility:
BE / ME graduates from Electronics, Electrical, Telecomm, Instrumentation Technology, Information Technology and Computer Science, with a min 60% aggregate.
Selection Process: Written test followed by interview.
Timing: Fulltime Monday to Friday 10.00 am to 6.00 pm
Fees: Rs.750 for Application Fees.
Certification: Advance Diploma in ASIC Design and Engineering upon successful completion of project.
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