Staircase Programs

 

 

Course Description

 

VLSI core subjects are taught to students during their engineering from third semester onwards. RV-VLSI has developed new course modules specifically for students who are still in their colleges. Through a series of staircase programs starting from third semester to seventh semester, one can augment his academic knowledge with a practical application of it by attending these staircase programs. It is coupled with a live project of industry standard in eights semester to gain hands-on application of the knowledge gained during engineering. These staircase programs are currently offered to Engineering Colleges who have a special arrangement with RV-VLSI.

 

 

Training Duration and Timings

 

5-10 day programs conducted during semester breaks between third and seventh semesters.

Contact RV-VLSI for further details.

 

 

Fee

 

Contact RV-VLSI for further details.

 

 

Who can benefit from this course?

 

  • Engineering students who want to gain knowledge and experience in VLSI
  • Engineering students aspiring for a career in the VLSI domain
  • Engineers who would like to pursue higher studies in India or abroad.

 

 

Eligibility

 

Eighth semester students interested in VLSI and Embedded Systems domain from the following branches: Electronics, Telecommunications, Electrical, Computer Science, Information Technology and Instrumentation Science.

 

 

Selection Process

Students are given admission through a special arrangement with their respective colleges in discussion with the department heads.

 

Contact RV-VLSI for further details.

 

 

Course Outline

 

Currently the following Staircase Programs are offered:

  • Logic Design for VLSI Engineers
  • CAD for VLSI Engineers
  • Verilog for VLSI Engineers
  • PERL for VLSI Engineers
  • Making of Nanometer VLSI chips
  • ASIC Implementation of VLSI chips RTL to GDS
  • Analog Design Techniques for VLSI Engineers

 

 

In an effort to maintain quality, RV-VLSI reserves the right to change or modify the course content and the duration of the course and the course fees.

 

 

A unit of Rashtreeya Sikshana Samiti Trust. All rights reserved, Copyright © RV-VLSI Design Center.