Introduction to Verilog (IHDL120)



Course Description


This class is a general introduction to the Verilog language and its use in programmable logic design, covering the basic constructs used in both the simulation and synthesis environments. By the end of this course, you will have a basic understanding of the Verilog module, data types, operators and assignment statements needed to begin creating your own designs, using both behavioral and structural approaches.



Course Fee


  • International (Corporate) Fee: $ 495

  • Domestic (Corporate) Fee: INR 5,000

  • Domestic (Student) Fee: INR 3,500


For further details contact RV-VLSI


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