Advanced Verilog HDL Design Techniques (IHDL230)
In this class,youwill learn & practice efficient coding techniques for writing synthesizable VHDL for programmable logic devices (FPGAs & CPLDs). While the concepts presented will mainly target Altera® FPGA devices using the Quartus® II software, many can be applied to other devices & synthesis tools.
International (Corporate) Fee: $ 495
Domestic (Corporate) Fee: INR 5,000
Domestic (Student) Fee: INR 3,500
For further details contact RV-VLSI
In an effort to maintain quality, RV-VLSI reserves the right to change or modify the course content and the duration of the course and the course fees.