You will be part of a core team of dedicated professionals committed to redefine VLSI training and raise the standards for professional training in VLSI.

Your experience in ASIC design across a wide technology will help create a new breed of professionals who will be industry ready. You will be proactive and work closely with the core team, industry professionals and experts from academia in designing the contents and identifying research areas.

Minimum 6 to 8 years of ASIC physical design experience. Must have hands on experience taping out chips in nanometer technologies. Experience in managing a team of 20 engineers. Excellent problem solving, mentoring and people skills.

Strong Back ground of logic design fundamentals, block and chip level Floor planning, power analysis, CTS, P&R , timing and Signal Integrity closure, DFT, STA, fullchip physical verification and extraction. Scripting Language with PERL, TCL, AWK, shell scripting is essential. Expert user of industry standard backend tools and timing analysis tools is a requirement. Exposure to Synthesis flow is a big plus.

BE/BTech in EE and or ME/MTech in Electronics and related branches Phd is added bonus Good understanding of the complete ASIC flow from concept to gds is a major plus Well versed in Perl/Tcl and Unix / Linux Published papers in international conferences and journals Participated in learning and development activities at work. Energetic and excellent communication skills.

Location: Bangalore

Email: info@rv-vlsi.com with Job Title in subject line.

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