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| VENKATESH PRASAD |
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Industry Experience : 16 years
BEL, Mentor Graphics-US, AMCC-US,
Conexant Systems-US
Area of Specialization : ASIC Backend,
Physical Verification and Extraction for
Multi Million Gate Designs, Custom Analog |
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Senior Vice President
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Sr. Vice President -- Corporate Alliance and placements
Experience : 35 yrs
Education : BE and MBA from FMS, Delhi |
Senior Design Engineers
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Sr. Design Engineer
Experience: ASIC Design and Verification - 9 plus years of experience in Design, Verification, Synthesis and Static timing analysis of ASICs, FPGAs in the field of SCSI, ATA, MMC Hard Disk Controller(HDC), PCI, ARM and SDRAM Controller
RTL Design and Verification
Education : B.E - Electronics and Communication
Area of Expertise :ASIC/FPGA Design and Verification in the field of SCSI, ATA, MMC Hard Disk Controller(HDC), PCI, ARM and SDRAM Controller |
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| Sr. Systems & CAD Support engineer |
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| GURURAJ RAO, M.Tech - CSc. |
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Experience :9 years of experience in teaching & industry.
Conducted DST sponsored skill improvement programmes in the areas of hardware and networking.
Conducted Cisco training programs and RHCE training programme.
Areas of Specialization:
Bash Shell/C Shell, AWK and Perl Scripting for automating system administrative tasks and management,viz Scripts to keep log entries of the files removed, Scripts to shut down Solaris/Linux Servers automatically triggered when UPS operating on critical conditions in battery mode, Managing resource configuration files, especially in C Shell, EDA tool automation & integration, EDA tool License Management.
Area(s) of Focus : Embedded System design, EDA Tool Automation, Networks.
Certification(s) : CCNA, Brainbench-Perl5.
Research Publications : Published a paper in international conference -ICEMC2 held at PESIT in Aug-4,5 2006 for the topic "Comparative Analysis of Five Wireless Adhoc Routing Protocols"
Education: M.Tech ( Computer Sc. & engg)
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| B G Savitha |
Physical Design Engineer
Experience : 2 Years
Education : M Tech in VLSI & Embedded sys.
Area of Expertise : Physical Design, Timing Analysis, Synthesis.
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| Tarakeshwar G P |
Design & Verification Engineer
Experience : 21 months(1.5+ yrs)
Education : BE
Area of Expertise : ASIC Verification |
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| CH V Rama Rao |
Design Engineer
Education : B Tech, Electronics and Communication
Area of Expertise : ASIC Implementation |
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| Subhash Sharma |
Physical Design
Experience : 2 Years
Education : B.E. (ECE) + M.Tech (IIT Bombay)
Area of Expertise : Physical Design, Timing Analysis, Synthesis.
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ANURADHA SRINIVASAN,
Engineering Manager |
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(Honorary Visiting Faculty)
Intel India Pvt. Ltd.
Experience : 20 years
Area of Specialization : ASIC Backend |
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| B.K. SRINATH, Technologist |
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(Honorary Visiting Faculty)
Texas Instruments India Pvt. Ltd.
Experience : 16 years
Area of Specialization : Library Design,
Memory Design, ASIC Backend |
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MOHAMMED HUSSIN,
Sr. Application Consultant |
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Synopsys India Pvt. Ltd.
Experience : 7 years
Area of Specialization : DFT, BIST |
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UMESH METKAR,
Sr. Application Consultant |
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Synopsys India Pvt. Ltd.
Experience : 9 years
Area of Specialization : ASIC Frontend,
Design Compiler, PT/PT-Si |
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